Clock Gating using latch and Logic gates
Clock Gating Today’s consumer demands more functionality, energy efficient devices and optimized power devices as time goes, so in order to optimize power of a device the simplest control technique is to shut off the clock of the sequential block of the device when there is no function required from that section for some duration.
Clock gating is a technique that can be used to control power dissipated by the clock net. In synchronous digital circuits the clock net is responsible for a significant part of power dissipation
RTL clock gating is the most common technique used for optimization and improving efficiency but still it leaves one question: how efficiently design clocks are gated. Gated clock is an easily accepted technique in order to optimize power and can be applied at system level, gate level and RTL. Clock gating can also save power by not clocking the register if there is no change in its state. Clock continuously consumes power because it toggles the register and associated logic gates. So, to reduce power consumption the clock gating shuts off the clock while the system maintains its current state.
Existing Clock Gating techniques :
AND Gate Based: It is one of the oldest clock gating techniques which was used for the simple sequential circuits. It is more prone to hazards and glitch. AND gate as a clock gating source and implemented the existing circuit of Clock gating technique. The input to the AND gate on the primary clock and the other input is an enable. The enable is used to control the primary clock. The output of the AND gate is considered a Global clock which is input to any sequential circuit.
This method is more prone to attack because of the direct connection of Enable. When enable is directly connected then the hazards of enable are directly transferred to the Global clock which in turn generates glitch in the clock signal. The circuit shown in figure below shows the circuit diagram of AND gate clock gating and figure below shows the waveform for the same circuit.
NOR gate based: It is the technique of clock gating when we want the positive edge of the clock to be working. It is also prone to glitch and hazards due to the possibility of glitch in enabled signals. NOR gate was used as a clock gating tool. This technique is efficient for positive end clock gating. The glitch and hazard problem still stays the same as it was in the case of AND gate based clock gating.
Figure below shows the circuit diagram of the same and figure below shows the waveform for NOR based clock gating.
LATCH based: Latch based technique can be designed for both positive latch as well as negative latch. It is less prone to glitch because of no direct connection with the enable to global clock. It can be designed using AND gate as well as NOR gate after the latch.
Proposed Model for clock gating technique: The new proposed approach as shown in below figure demonstrates the circuit diagram of two types namely: Clock gate using negative latch and clock gating using positive latch.
In the circuit shown below the power useless power consumption decreases in such a way that even when the target device clock is in ON position , and the controlling device clock is in off position and also when the target device’s clock is OFF. This way power dissipation will decrease and we can save more power on power constrained circuits by avoiding unnecessary switching at the clock network.
For understanding the working of the circuit consider figure below, an input signal named En(enable) is provided to the latch. When En turns to ‘1’ at that time GEN signal is ‘0’ GEN signal is the output of the latch which works as an input to the XNOR gate, XNOR will produce x = “0” which serves as the input to the first clock generating logic that generates a clock pulse which have global clock as an input. At the other input of or gate. This logic will then generate a clock pulse that will drive the controlling latch when ‘X’ turns to “0’.
For the next clock pulse , When GEN signal Changes to “1”, the second clock generation logic which is an AND gate which has GEN signal and Global Clock as “GLCK” at its input and, when GEN signal goes”1” it generates a clock pulse that goes to the target device. Since the GEN signal is “1” the XNOR gate will produce X = “1”(high) thus OR will produce at CCLK(Control Clock ) constant high until En turns to “0”(low). In This manner GCLK will be continuously running and CCLK will be in a constant “1” state , that means latch will hold its state without any switching.
The circuit shown in figure below also executes a similar sequence of operation as explained for the circuit shown in figure. an input signal named En(enable) is provided to the latch. When En turns to ‘1’ at that time GEN signal is ‘0’ GEN signal is the output from the latch which works as an input to the AND gate, AND will produce x = “1” which is input to the first clock generation logic that generates a clock pulse which have global clock as an input. At the other input of or gate. This logic will produce a clock pulse that will push the controlling latch when ‘X’ turns to “0’.
For the next clock pulse , When GEN signal turns to “1”, the second clock generation logic which is an OR gate which has Q and Global Clock as “GCLK” at its input and, when Q goes”0” it generates a clock pulse that shifts to the target device. Since the GEN signal is “1” the XOR gate will produce X = “0” thus OR will produce at CCLK(Control Clock ) constant low until En turns to “0”. This way GCLK(Global clock ) will be running and CCLK(Controlling clock) will be at a constant “0” state , that means latch will hold its state without any switching.
Disadvantage of Proposed the Model
As the main motive of proposing a new model of clock technique is to decrease the net power consumption but when this clock gating technique will be used for small circuits it will lead to power loss, whereas when the global clock is connected to a large sequential circuit the overall power dissipation will decrease and the immunity against glitch also increases.
As the complete clock circuit has multiple sequential and combinational circuits the clock delay also increases by one clock signal so total delay when compared to non clock gated signal is 2 clock signal. So due to this reason it cannot be used for the clock gating technique for a device which has a clock as its most important substitute.
Comparative study of different model: